Current radar systems are generally mission specific, expensive, and not reconfigurable. A radar system using programmable filtering and large instantaneous bandwidth may provide flexibility in system design, which may reduce system cost and deployment cycle. As the point of digitization in a radar detection system moves closer to the antenna, more power is being consumed due to processing of wide bandwidth signals. Analog signal processing at the antenna is more power efficient than digital signal processing.
A conventional finite impulse response (FIR) filter architecture may not be an ideal choice for analog signal processing. FIG. 1 illustrates a conventional N-tap FIR filter 100, which includes N (an integer greater than 1) sample and hold blocks 102, coefficient multipliers 104, and voltage accumulators (or voltage adders) 106. Each sample and hold block 102 introduces noise and distortions, which may result in significant distortion of the analog input signal by the time it reaches the Nth tap. Further, the coefficient multipliers 104 and the accumulators 106 introduce additional noise and nonlinearities, which further distort the analog voltages and limit the performance of the FIR filter (e.g., in terms of dynamic range and signal-to-noise ratio). Furthermore, generating the coefficient for each of the coefficient multipliers 104 may require a separate digital-to-analog converter (DAC), which increases the power consumption of the FIR filer 100.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.